1. Field of the Invention
This invention relates to multi-core processors, and more particularly, to access of the multiple cores for testing.
2. Description of the Related Art
Processor designers use many different techniques to increase the speed at which information can be processed. One technique that is increasingly implemented on new processor designs is the use of multiple, identical cores on the same processor. Through the use of multiple identical processor cores, many processing tasks can be divided to allow each core to process a portion of the whole.
As with single core designs, multiple core processors must be tested in order to ensure their readiness for shipping to a customer. A portion of the testing can be accomplished using scan technology. Scan testing utilizes chains of scan elements coupled serially together (‘scan chains’). A scan chain is created using the flip-flops (or latches or other clocked storage devices) of a processor. The output of a given flip-flop is coupled to the input of another flip-flop. A large number of flip-flops are connected in this manner, forming a scan chain that passes through the internal logic of the processor. The scan chain may be thought of as a serial shift register, in which values are shifted from one register flop to the next.
In order to test the processor logic using a scan chain, stimulus scan data (i.e. the test data, the test vector, or scan input data) is shifted into the chain, loading each element of the chain with a predetermined value. Following the initial loading, the circuit is then reverted to its normal operating mode, allowing the individual circuits to respond to the scan data. After allowing the circuits a sufficient time to respond, the circuit response scan data (i.e. scan output data) is shifted out of the scan chain, where it is compared with expected results to determine whether the chip is faulty.
In multiple core processors, each identical core may include one or more identical scan chains. Since the cores and the scan chains are identical, it follows that each core, when free of defects, should exhibit a response to a test vector that matches that of other defect-free cores. However, to ensure the processor overall is defect-free, each of the cores must be tested independently of one another. This requirement can greatly increase the time required to conduct a test of the entire processor if the cores are to be tested consecutively. Alternatively, this requirement can increase the required signal space with regard to the input/output pins of the processors in order to provide access to scan chains for each core. Since each core may require multiple scan chains, and since each scan chain requires signal space for scan clock signals, commands, scan data, and so forth, the required signal space can be quite large. Thus, a tradeoff between test time and signal space may be a consequence necessitated by scan testing of processors having multiple identical cores.